This invention relates to an improved logic arrangement suitable for incorporation in an integrated semiconductor device.
Included in the types of digital logic circuits which are particularly amenable to fabrication as monolithic integrated circuit networks are transistor-transistor logic (TTL) circuits. An example of such a circuit is taught in U.S. Pat. No. 3,629,609 issued to R. A. Pedersen et al. on Dec. 21, 1971. Operating characteristics of TTL circuits which are often important in applications include switching speed, response to load variations, compatibility of voltage levels, and immunity to spurious signals.
The immunity of logic circuits to spurious signals is generally referred to in terms of the circuit's noise margins. These noise margins are defined relative to a threshold which is itself defined as the level of the voltage applied at the input of the gate required to produce the same voltage level at the output of that gate.
The first noise margin, or low-level noise margin, is the difference between the maximum low-level input signal voltage and the threshold voltage. Analogously, the second, or high-level noise margin, is the difference between the minimum high-level voltage and the threshold voltage. Further, the signal swing of the circuit is defined as the difference between the maximum high-level voltage and the minimum low-level input signal voltage.
To improve the operation of TTL circuits it is desirable to have increased switching speed and relatively quick charging of any output capacitance. It is further desirable to attain these objectives while maintaining voltage levels and noise margins compatible with prevalent TTL circuits.
An example of a TTL circuit which includes a favorable switching speed and a relatively fast charging of output capacitance is U.S. Pat. No. 3,571,616 issued to J. R. Andrews on Mar. 23, l971. The Andrews patent discloses a circuit which uses a pull-up transistor to reduce the resistance of the charging path of the output capacitance. However, along with reduced resistance in the charging path, the circuit of the Andrews patent has some increased voltage levels. As a result, the voltage levels may not be compatible with certain other TTL circuits. It would be desirable to achieve the faster switching possible through the use of a pull-up transistor without the necessity to change voltage levels.